The integrated circuit (IC) design is more challenging when semiconductor technologies are continually progressing to smaller feature sizes, such as 65 nanometers, 45 nanometers, and below. The performance of a chip design is seriously influenced by the control of resistance/capacitance (RC), timing, leakage, and topology of the metal/dielectric inter-layers.
To enhance the imaging effect when a design pattern is transferred to a wafer, optical proximity correction (OPC) is indispensable. The design pattern is adjusted to generate an image on the wafer with improved resolution.
However, patterning corner rounding is still an issue in various existing methods. Traditional methods do not take enough care on corner rounding. For N28 nodes and below, the severity of corner rounding generates many side effects with significant impact, which is unacceptable in term of device performance, quality and reliability. For example, the corner rounding generates unexpected patterning shape that may cause short-circuit, open-circuit, RC variation, device performance drift, etc. These side effects cause more serious problems for the coming nodes in the near future.
Therefore, what is needed is a method for IC design and mask making to efficiently and significantly reduce patterning corner rounding.